Dr Roopak Sinha

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Senior Lecturer and Academic Leader (Master of Service-Oriented Computing)

Phone: +64-9-9219999 extension 6256

Email: rsinha@aut.ac.nz

Physical Address:
School of Computer and Mathematical Sciences
AUT Tower,
2-14 Wakefield Street,
Auckland 1010
New Zealand

Links to relevant web pages:


PhD (Electrical and Electronics Engineering), University of Auckland

PGCert Academic Practice, University of Auckland

Master of Commercialisation and Entrepreneurship, University of Auckland (Pursuing)

Teaching Areas:

Software Engineering

Computer Science

Embedded systems

Computer systems


  1. Roopak Sinha, Partha S Roop, and Samik Basu. Correct-by-Construction Approaches for SoC Design. Springer, 2013
Book Chapters
  1. Markus Ortel, Marc Malot, Andreas Baumgart, Jan Steffen Becker, Ralf Bogusch, Stefan Farfeleder, Nora Gerber, Oystein Haugen, Stefan Hausler, Bernhard Josko, Jason Mansell, Andreas Mitschke, Roopak Sinha, Tor Stalhane, Niina Uusitalo, and Philip Rehkop. Requirements engineering. In Ajitha Rajan and Thomas Wahl, editors, CESAR: Cost-efficient Methods and Processes for Safety-relevant Embedded Systems, number 978-3709113868. Springer, 2013

Refereed Journal Articles

  1. R. Sinha, P. Roop, and P. Ranjitkar. Virtual traffic lights+: A robust, practical, and functionally safe intelligent transportation system. Transport Research Records, 2013
  2. R. Sinha, P.S. Roop, and S. Basu. SoC design approach using convertibility verification. EURASIP Journal on Embedded Systems, 2008:1, 2008
  3. R. Sinha, P.S. Roop, and S. Basu. A model checking approach to protocol conversion. Electronic Notes in Theoretical Computer Science, 203(4):81–94, 2008
  4. S. Basu, P.S. Roop, and R. Sinha. Local module checking for CTL specifications. Electronic Notes in Theoretical Computer Science, 176(2):125–141, 2007
  5. R. Sinha, P.S. Roop, and B. Khoussainov. Adaptive verification using forced simulation. Electronic Notes in Theoretical Computer Science, 141(3):171–197, 2005

Conference Submissions

  1. Zeeshan Ejaz Bhatti, Roopak Sinha, and Partha Roop. Unified functional safety assessment of industrial automation systems. In IEEE International Conference on Emerging Technology and Factory Automation (ETFA), September 2013 (Accepted for publication)
  2. Roopak Sinha, Partha Roop, Prakash Ranjitkar, Junbo Zeng, and Xingchen Zhu. Model-based design of coordinated traffic controllers. In 20th ITS World Congress, October 2013
  3. S. Andalam, R. Sinha, P. Roop, A. Girault, and J. Reineke. Precise timing analysis for direct-mapped caches. In 50th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 2013 (Acceptance rate: 21%)
  4. R. Sinha, P. Roop, and P. Ranjitkar. Virtual traffic lights+: A robust, practical, and functionally safe intelligent transportation system. In Transport Research Board (TRB), 92nd Annual Meeting. TRB, 2013 (Acceptance rate: 50%)
  5. R. Sinha, P.S. Roop, Z. Salcic, and S. Basu. Correct-by-construction multi-component SoC design. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pages 647–652. IEEE, 2012 (Acceptance rate: 25%)
  6. Z.E. Bhatti, R. Sinha, and P.S. Roop. Observer based verification of IEC 61499 function blocks. In Industrial Informatics (INDIN), 2011 9th IEEE International Conference on, pages 609–614. IEEE, 2011 
  7. M. Kuo, R. Sinha, and P. Roop. Efficient WCRT analysis of synchronous programs using reachability. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 480–485. IEEE, 2011 (Acceptance rate: 22.6%)
  8. S. Andalam, R. Sinha, and P.S. Roop. Environment modelling for tighter timing analysis of synchronous programs. In Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on, pages 150–155. IEEE, 2011
  9. R. Sinha, P.S. Roop, S. Basu, and Z. Salcic. Multi-clock soc design using protocol conversion. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 123–128. European Design and Automation Association, 2009 (Acceptance rate: 23%)
  10. P. Roop, A. Girault, R. Sinha, and G. Goessler. Specification enforcing refinement for convertibility verification. In Application of Concurrency to System Design, 2009. ACSD’09. Ninth International Conference on, pages 148–157. IEEE, 2009 (Acceptance rate 50%)
  11. R. Sinha, P.S. Roop, and S. Basu. A module checking based converter synthesis approach for SoCs. In VLSI Design, 2008. VLSID 2008. 21st International Conference on, pages 492–501. IEEE, 2008 (Acceptance rate 25%)

Completed Theses and Reports

  1. Sidharta Andalam. Predictable Platforms for Safety-Critical Embedded Systems. PhD thesis, University of Auckland, 2013 (Role: Adviser)
  2. Gareth Darcy Shaw. Reliable model-driven engineering using IEC 61499. PhD thesis, University of Auckland, 2013 (Role: Adviser)
  3. Pranav Chandnani and Roopak Sinha. Modelling and verification of intelligent transportation systems in C, Summer Project Report, University of Auckland, 2013. (Role: Supervisor)
  4. Roopak Sinha. Automated techniques for formal verification of SoCs. PhD thesis, University of Auckland, 2009
  5. S. Chen. Generalised adapter synthesis using forced model checking. Master’s thesis, University of Auckland, 2008. (Role: Co-supervisor)


2013 Faculty of Engineering Teaching Excellence Award (Early Career), The University of Auckland.
2012 Faculty of Engineering Top Teacher Award, The University of Auckland.
2007 Best Paper Award. Foundations of Embedded Software and Component-based Software Architectures, Vienna, Austria.